The present invention relates to a method and apparatus for generating one or more reference currents, and, more particularly, to an integrated reference current generator that operates in conjunction with an external reference resistor. This application is related to my co-pending application entitled "LIGHT-EMITTING DIODE ARRAY CURRENT POWER SUPPLY INCLUDING SWITCHED CASCADE TRANSISTORS", Ser. No. 07/948,274.
Reference current generators are frequently used in integrated circuits for generating a multiplicity of bias currents that track with temperature, process variations, and transistor gain. Three embodiments of known reference circuits are shown in FIGS. 1-3, although other embodiments are known. Referring now to FIG. 1, reference circuit 10 includes an operational amplifier ("op-amp") 14, and multiple N-channel field-effect transistors ("FETs") 16-20 for generating multiple sink bias currents at the drains of each respective FET. Due to the feedback from node 22 at the drain of FET 16 to the non-inverting input of op-amp 14 and high loop gain, op-amp 14 imposes a voltage at the output node 26 such that the voltage at the inverting and non-inverting terminals is approximately equal. Since op-amp 14 has its inverting input connected to a reference voltage designated "V.sub.REF ", the voltage at its non-inverting input is also equal to V.sub.REF. A reference resistance R.sub.REF is coupled to the non-inverting input of op-amp 14 and therefore a current, designated "I.sub.REF " is generated with a magnitude equal to (V.sub.CC -V.sub.REF) /R.sub.REF. The reference resistance block 80 can be either a simple internal integrated resistance, such as a polysilicon or thin-film resistor, or a precision external resistance coupled to the circuit 10 through an external bonding pad 12. The gate-to-source voltage of FET 16 is impressed across the gate and source of output transistors 18 and 20, producing a current through each substantially similar to the reference current, assuming equally sized devices.
Another embodiment 40 of a reference current generator circuit is shown in FIG. 2. In FIG. 2, reference circuit 40 includes P-channel output FETs 28-32 to provide a multiplicity of source output bias currents. The output of op-amp 14 drives the gates of FETs 28, 30, and 32. In addition, the sources of FETs 28-32 are coupled together and to a source of positive supply voltage, VCC. As in reference circuit 10, the reference voltage V.sub.REF is coupled to the inverting input of op-amp 14. The drain of FET 28 is coupled to the non-inverting input of op-amp 14 because of the inverted gain from the gate to the drain of FET 28. The non-inverting input of op-amp 14 is also coupled to the reference resistance R.sub.REF through bonding pad 12. The op-amp 14 impresses the reference voltage V.sub.REF across reference resistance R.sub.REF, which produces a reference current I.sub.REF equal to V.sub.REF /R.sub.REF. The gate-to-source voltage of FET 28 is impressed across the gate and source of output transistors 30 and 32. Circuit 40, and other similar circuits, are commonly used as LED drivers because each output driver is independent from the other. If one of the bias currents is interrupted or made inaccurate, it has no effect on the other bias currents.
Note that in reference circuits 10 and 40 reference current I.sub.REF flows directly through output transistors 16 and 28. The drain currents of transistor 16 and 28 cannot be used directly but are used to generate the reference gate-to-source voltage. If output transistor sizes are equal, output bias currents I.sub.18 -I.sub.20 and I.sub.30 -I.sub.32 are both substantially equal to I.sub.REF. If output transistor sizes are unequal, output currents are proportional to the respective W/L ratios of the output transistors.
A third embodiment 50 of a typical reference circuit is shown in FIG. 3. Reference circuit 50 includes a single N-channel FET 16, the drain current of which is used to create a reference gate-to-source voltage through P channel FET 34. In circuit 50, op-amp 14 drives the gate of N-channel FET 16, with the non-inverting input connected to V.sub.REF. The inverting input is coupled to the source of FET 16, which is coupled to the reference resistance R.sub.REF. The generated reference current I.sub.REF is equal to V.sub.REF /R.sub.REF and flows through N-channel FET 16 and P-channel current reference FET 34. The drain of FET 16 is connected to the coupled drain and gate of P-channel current reference FET 34, to generate a reference gate-to-source voltage between node 78 and VCC. The gates of output FETs 30 and 32 are coupled to node 78 to replicate the reference current. Circuit 50 is similar to circuit 40 except for the exact manner in which the reference gate-to-source voltage is generated.
In reference circuits 10, 40, and 50, as well as many other such circuits, a reference voltage, V.sub.REF, and a reference impedance, R.sub.REF, are known. The desired current output or outputs are one or more copies of a reference current equal or proportional to I.sub.REF. The ability to accurately control the two known quantities directly determines the accuracy of the resulting desired output reference current I.sub.REF. However, practical limitations in the fabrication and implementation of the reference circuit can have an adverse affect on accuracy of one or both of these quantities. FIG. 4 shows a simplified circuit 40 in which an external precision reference resistance is used. In many integrated circuits, it is desirable to protect output pins with an internal series electrostatic discharge ("ESD") protection resistor, R.sub.ESD. In addition to the ESD protection resistor, a parasitic resistance R.sub.s exists as well. The parasitic and ESD protection resistor R.sub.s are both in series with the external reference resistor and are sources of reference current error. The value of the reference current is therefore modified according to the equation V.sub.REF /(R.sub.REF +R.sub.ESD +R.sub.S). The output reference current is therefore not equal to the nominal design current of V.sub.REF /R.sub.REF. In addition, since the internal resistance R.sub.ESD and R.sub.s can vary widely with process variations and temperature, the corresponding reference current and generated output bias currents can also vary.
Another limitation of circuits 10, 40, and 50 is that they have one operational mode--either a relatively inaccurate internal reference mode or a relatively accurate external resistance mode. However, due to the practical limitations of producing integrated circuit resistances, it is desirable to provide for both an internal and external mode, especially if the internal resistance falls outside a predetermined acceptable resistance tolerance. In addition, a third mode is desired that allows the user to determine whether the internal inaccurate mode falls within the acceptable range of resistances.
It is desirable, therefore, to provide a current generator reference circuit in which undesirable variations in output current due to internal series resistance is minimized. Furthermore, it is also desirable to provide a reference circuit having two or more operational modes for use with the external or internal reference resistor, or for test and measurement purposes.